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Microarchitectures: Difference between revisions

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| 20
| 20
| 4.77--10 MHz
| 4.77--10 MHz
| none
| x86-16
| Designed for use with 8-bit externals
| Designed for use with 8-bit externals
Used in IBM PC-5150 / XT-5160 / PCjr-4860
Used in IBM PC-5150 / XT-5160 / PCjr-4860
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| 4--12.5 MHz
| 4--12.5 MHz
| 8086-2
| 8086-2
| Introduced protected mode
| Introduced protected mode/MMU
Used in the IBM AT-5170
Used in the IBM AT-5170
|-
|-
|}
|}
===Instruction sets===
===Instruction sets===
* x86-16: The granddaddy of 'em all
* 8086-2: Added ENTER/LEAVE, PUSHA/POPA, INS/OUTS
* 8086-2: Added ENTER/LEAVE, PUSHA/POPA, INS/OUTS



Revision as of 17:11, 20 January 2011

Microarchitecture is defined as those elements of a CPU design which are, to first order, invisible to application programmers (ie, not part of the instruction set). Those elements which are visible comprise the architecture.

x86 μarchitectures

FIXME: add early clones (NEC V20/V30, etc), AMD, VIA, Cyrix etc...

Name Maker Date Process (min) Package ALU/data bits Addr bits Clock(s) ISA Notes
8086 Intel 1978 3.2 μm 40-pin DIP 16 20 4.77--10 MHz x86-16 Segmented memory

Optional 80-bit 8087 FP coprocessor

8088 Intel 1979 3.2 μm (?) 40-pin DIP

44-pin PLCC

16/8 20 4.77--10 MHz x86-16 Designed for use with 8-bit externals

Used in IBM PC-5150 / XT-5160 / PCjr-4860

80186 Intel 1982 2.6 μm 68-pin PLCC
68-pin PGA
100-pin PQFP
16 20 6--25 MHz 8086-2 Designed for embedded systems (clock, PIC, DMA on-die)
80286 Intel 1982 1.5 μm 68-pin PGA
68-pin CLCC
68-pin PLCC
16 24 4--12.5 MHz 8086-2 Introduced protected mode/MMU

Used in the IBM AT-5170

Instruction sets

  • x86-16: The granddaddy of 'em all
  • 8086-2: Added ENTER/LEAVE, PUSHA/POPA, INS/OUTS

References