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Transmeta processors: Difference between revisions

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[[File:Transmeta-corp-logo.JPG|thumb|right|Transmeta Corporation logo]]
* [[:File:Tm8300tm8600.pdf|TM8300/TM8600 product spec]]
* [[:File:Tm8300tm8600.pdf|TM8300/TM8600 product spec]]
* [[:File:Tm3200.pdf|TM3200 product spec]]
* [[:File:Tm3200.pdf|TM3200 product spec]]
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{| border="1"
{| border="1"
! Family
! Family
! Core
! Model
! Model
! Interface
! Interface
! Frequencies
! Frequencies
! L1 Cache(s)
! L1 Caches
! L2 Cache
! L2 Cache
! TLB
! TLB
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! Peripherals
! Peripherals
|-
|-
| rowspan="2" | Crusoe
| rowspan="2" | Crusoe (128-bit + MMX)




[[File:Tm5400_chip.jpg|thumb|caption="TM5400"]]
[[File:Tm5400_chip.jpg|thumb|right|TM5400]]
| rowspan="2" | 128-bit
 
2x ALU, 1x Load/Store
 
1x Branch, 1x FP/MM
| TM3200
| TM3200
| BGA-474
| BGA-474
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| 64K 8-associative code,
| 64K 8-associative code,
64K 16-associative data  
64K 16-associative data  
| 256K unified
| 256K 4-associative unified
| 256 entries, 4-associative
| 256 entries, 4-associative
| SDR/DDR SDRAM 66--133MHz,
| SDR/DDR SDRAM 66--133MHz,
DDR SDRAM 100--133MHz
DDR SDRAM 100--133MHz
| 33MHz 32-bit PCI1
| 33MHz 32-bit PCI
|-
|-
| ROWSPAN="5" | Efficeon
| ROWSPAN="5" | Efficeon (256-bit + SSE2)
 
 
[[File:KL_Transmeta_Efficeon_8600.jpg|thumb|right|TM8600]]
2x ALU, 2x Load/Store/Add


2x Execute, 2x FP/MM/SSE/SSE2


[[File:KL_Transmeta_Efficeon_8600.jpg|thumb|caption="TM8600"]]
1x Branch, 1x Alias, 1x Control
| rowspan="5" | 256-bit + SSE2
| TM8300
| TM8300
| BGA-783
| BGA-783
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|}
|}
==See Also==
==See Also==
* The [http://www.sandpile.org/docs/tmta.htm sandpile] has a fine Transmeta collection
* The [http://www.sandpile.org/docs/tmta.htm sandpile] has a fine Transmeta doc collection
** And a [http://www.sandpile.org/impl/crusoe.htm Crusoe] reference
** Not to mention an [http://www.sandpile.org/impl/efficeon.htm Efficeon] reference
* A good [http://hubpages.com/hub/Ball-Grid-Array-Guide BGA page] at HubPages.
[[CATEGORY: Hardware]]
[[CATEGORY: X86]]