Transmeta processors: Difference between revisions

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(Created page with '{| border="1" ! Family ! Model ! Frequencies ! L1 Cache(s) ! L2 Cache |- | Crusoe | | | | |- | ROWSPAN="3" | Efficeon | TM8600 | | | |- | TM8620 | | | |- | TM8800 | | | | |}')
 
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{| border="1"
{| border="1"
! Family
! Family
! Core
! Model
! Model
! Frequencies
! Frequencies
! L1 Cache(s)
! L1 Cache(s)
! L2 Cache
! L2 Cache
! Memory interface
|-
|-
| Crusoe
| rowspan="2" | Crusoe
|
| rowspan="2" | 128-bit
|
| TM3200
|
| 333--400MHz
|
| 64K code, 32K data
| none
| SDRAM
|-
| TM5400
| 500--700MHz
| 64K code, 64K data
| 256K unified
| SDRAM, DDR SDRAM
|-
|-
| ROWSPAN="3" | Efficeon
| ROWSPAN="3" | Efficeon
| rowspan="3" | 256-bit
| TM8600
| TM8600
|
|
|
|
|
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|-
|-
| TM8620
| TM8620
|
|
|
|
|

Revision as of 01:13, 15 April 2010

Family Core Model Frequencies L1 Cache(s) L2 Cache Memory interface
Crusoe 128-bit TM3200 333--400MHz 64K code, 32K data none SDRAM
TM5400 500--700MHz 64K code, 64K data 256K unified SDRAM, DDR SDRAM
Efficeon 256-bit TM8600
TM8620
TM8800