Transmeta processors: Difference between revisions

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| SDRAM, DDR SDRAM
| SDRAM, DDR SDRAM
|-
|-
| ROWSPAN="3" | Efficeon
| ROWSPAN="4" | Efficeon
| rowspan="3" | 256-bit
| rowspan="4" | 256-bit + SSE2
| TM8300
| 900MHz--1.1GHz
| 128K code, 64K data
| 512K unified
| 100--166MHz DDR
|-
| TM8600
| TM8600
|
| 900MHz--1.1GHz
|
| 128K code, 64K data
|
| 1M unified
|
| 100--166MHz DDR
|-
|-
| TM8620
| TM8620

Revision as of 01:17, 15 April 2010

Family Core Model Frequencies L1 Cache(s) L2 Cache Memory interface
Crusoe 128-bit TM3200 333--400MHz 64K code, 32K data none SDRAM
TM5400 500--700MHz 64K code, 64K data 256K unified SDRAM, DDR SDRAM
Efficeon 256-bit + SSE2 TM8300 900MHz--1.1GHz 128K code, 64K data 512K unified 100--166MHz DDR
TM8600 900MHz--1.1GHz 128K code, 64K data 1M unified 100--166MHz DDR
TM8620
TM8800