Transmeta processors: Difference between revisions

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* [[:File:Tm8300tm8600.pdf|TM8300/TM8600 product spec]]
* [[:File:Tm8300tm8600.pdf|TM8300/TM8600 product spec]]
* [[:File:Tm3200.pdf|TM3200 product spec]]


{| border="1"
{| border="1"
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! L1 Cache(s)
! L1 Cache(s)
! L2 Cache
! L2 Cache
! TLB
! Memories
! Memories
! Peripherals
! Peripherals
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| rowspan="2" | 128-bit
| rowspan="2" | 128-bit
| TM3200
| TM3200
|
| BGA-474
| 333--400MHz
| 366--400MHz
| 64K code, 32K data
| 64K 8-associative code, 32K 8-associative data
| none
| none
| SDRAM
| 256 entries, 4-associative
|
| SDR SDRAM 66--133MHz
| 33MHz 32-bit PCI
|-
|-
| TM5400
| TM5400
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| rowspan="4" | 256-bit + SSE2
| rowspan="4" | 256-bit + SSE2
| TM8300
| TM8300
|
| BGA-783
| 900MHz--1.1GHz
| 900MHz--1.1GHz
| 128K code, 64K data
| 128K code, 64K data
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|-
|-
| TM8600
| TM8600
|
| BGA-783
| 900MHz--1.1GHz
| 900MHz--1.1GHz
| 128K code, 64K data
| 128K code, 64K data
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|-
|-
| TM8620
| TM8620
|
|  
|
| 900MHz--1.1GHz
|
|
|
|
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| TM8800
| TM8800
|
|
|
| 1.1GHz--1.7GHz
|
|
|
|

Revision as of 01:37, 15 April 2010

Family Core Model Interface Frequencies L1 Cache(s) L2 Cache TLB Memories Peripherals
Crusoe 128-bit TM3200 BGA-474 366--400MHz 64K 8-associative code, 32K 8-associative data none 256 entries, 4-associative SDR SDRAM 66--133MHz 33MHz 32-bit PCI
TM5400 500--700MHz 64K code, 64K data 256K unified SDRAM, DDR SDRAM
Efficeon 256-bit + SSE2 TM8300 BGA-783 900MHz--1.1GHz 128K code, 64K data 512K unified 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8600 BGA-783 900MHz--1.1GHz 128K code, 64K data 1M unified 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8620 900MHz--1.1GHz
TM8800 1.1GHz--1.7GHz

See Also

  • The sandpile has a fine Transmeta collection