Transmeta processors: Difference between revisions

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==See Also==
==See Also==
* The [http://www.sandpile.org/docs/tmta.htm sandpile] has a fine Transmeta collection
* The [http://www.sandpile.org/docs/tmta.htm sandpile] has a fine Transmeta collection

Revision as of 01:47, 15 April 2010

Family Core Model Interface Frequencies L1 Cache(s) L2 Cache TLB Memories Peripherals
Crusoe 128-bit TM3200 BGA-474 366--400MHz 64K 8-associative code, 32K 8-associative data none 256 entries, 4-associative SDR SDRAM 66--133MHz 33MHz 32-bit PCI
TM5400 500--700MHz 64K code, 64K data 256K unified 256 entries, 4-associative SDRAM, DDR SDRAM
Efficeon 256-bit + SSE2 TM8300 BGA-783 900MHz--1.1GHz 128K 4-associative code, 64K 8-associative data 512K 4-associative unified 256 entries, 4-associative 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8600 BGA-783 900MHz--1.1GHz 128K 4-associative code, 64K 8-associative data 1M 4-associative unified 256 entries, 4-associative 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8620 BGA-592 900MHz--1.1GHz 128K 4-associative code, 64K 8-associative data 1M 4-associative unified 256 entries, 4-associative 400MHz HyperTransport, AGP 1x/2x/4x
TM8800 BGA-783 1.1GHz--1.7GHz 128K 4-associative code, 64K 8-associative data 1M 4-associative unified 256 entries, 4-associative 400MHz HyperTransport, AGP 1x/2x/4x
TM8820 BGA-592 1.1GHz--1.7GHz 128K 4-associative code, 64K 8-associative data 1M 4-associative unified 256 entries, 4-associative 400MHz HyperTransport, AGP 1x/2x/4x

See Also

  • The sandpile has a fine Transmeta collection