Transmeta processors: Difference between revisions

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| rowspan="2" | Crusoe
| rowspan="2" | Crusoe


[[File:Tm5400_chip.jpg|thumb]]
 
[[File:Tm5400_chip.jpg|thumb|caption="TM5400"]]
| rowspan="2" | 128-bit
| rowspan="2" | 128-bit
| TM3200
| TM3200
Line 42: Line 43:




[[File:KL_Transmeta_Efficeon_8600.jpg|thumb]]
[[File:KL_Transmeta_Efficeon_8600.jpg|thumb|caption="TM8600"]]
| rowspan="5" | 256-bit + SSE2
| rowspan="5" | 256-bit + SSE2
| TM8300
| TM8300

Revision as of 02:02, 15 April 2010

Family Core Model Interface Frequencies L1 Cache(s) L2 Cache TLB Memories Peripherals
Crusoe


caption="TM5400"
128-bit TM3200 BGA-474 366--400MHz 64K 8-associative code,

32K 8-associative data

none 256 entries, 4-associative SDR SDRAM 66--133MHz 33MHz 32-bit PCI
TM5400 BGA-474 500--700MHz 64K 8-associative code,

64K 16-associative data

256K unified 256 entries, 4-associative SDR/DDR SDRAM 66--133MHz,

DDR SDRAM 100--133MHz

33MHz 32-bit PCI1
Efficeon


caption="TM8600"
256-bit + SSE2 TM8300 BGA-783 900MHz--1.1GHz 128K 4-associative code,

64K 8-associative data

512K 4-associative unified 256 entries, 4-associative 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8600 BGA-783 900MHz--1.1GHz 128K 4-associative code,

64K 8-associative data

1M 4-associative unified 256 entries, 4-associative 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8620 BGA-592 900MHz--1.1GHz 128K 4-associative code,

64K 8-associative data

1M 4-associative unified 256 entries, 4-associative 100--200MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8800 BGA-783 1.1GHz--1.7GHz 128K 4-associative code,

64K 8-associative data

1M 4-associative unified 256 entries, 4-associative 100--200MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8820 BGA-592 1.1GHz--1.7GHz 128K 4-associative code,

64K 8-associative data

1M 4-associative unified 256 entries, 4-associative 100--200MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x

See Also

  • The sandpile has a fine Transmeta collection