Transmeta processors: Difference between revisions

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** And a [http://www.sandpile.org/impl/crusoe.htm Crusoe] reference
** And a [http://www.sandpile.org/impl/crusoe.htm Crusoe] reference
** Not to mention an [http://www.sandpile.org/impl/efficeon.htm Efficeon] reference
** Not to mention an [http://www.sandpile.org/impl/efficeon.htm Efficeon] reference
* A good [http://hubpages.com/hub/Ball-Grid-Array-Guide BGA page] at HubPages.
[[CATEGORY: Hardware]]
[[CATEGORY: Hardware]]
[[CATEGORY: X86]]
[[CATEGORY: X86]]

Revision as of 01:17, 15 April 2010

Family Model Interface Frequencies L1 Caches L2 Cache TLB Memories Peripherals
Crusoe (128-bit + MMX)


TM5400
TM3200 BGA-474 366--400MHz 64K 8-associative code,

32K 8-associative data

none 256 entries, 4-associative SDR SDRAM 66--133MHz 33MHz 32-bit PCI
TM5400 BGA-474 500--700MHz 64K 8-associative code,

64K 16-associative data

256K 4-associative unified 256 entries, 4-associative SDR/DDR SDRAM 66--133MHz,

DDR SDRAM 100--133MHz

33MHz 32-bit PCI
Efficeon (256-bit + SSE2)


TM8600
TM8300 BGA-783 900MHz--1.1GHz 128K 4-associative code,

64K 8-associative data

512K 4-associative unified 256 entries, 4-associative 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8600 BGA-783 900MHz--1.1GHz 128K 4-associative code,

64K 8-associative data

1M 4-associative unified 256 entries, 4-associative 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8620 BGA-592 900MHz--1.1GHz 128K 4-associative code,

64K 8-associative data

1M 4-associative unified 256 entries, 4-associative 100--200MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8800 BGA-783 1.1GHz--1.7GHz 128K 4-associative code,

64K 8-associative data

1M 4-associative unified 256 entries, 4-associative 100--200MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8820 BGA-592 1.1GHz--1.7GHz 128K 4-associative code,

64K 8-associative data

1M 4-associative unified 256 entries, 4-associative 100--200MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x

See Also