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Transmeta processors

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Revision as of 05:30, 15 April 2010 by Dank (talk | contribs)
Family Core Model Interface Frequencies L1 Cache(s) L2 Cache Memories Peripherals
Crusoe 128-bit TM3200 333--400MHz 64K code, 32K data none SDRAM
TM5400 500--700MHz 64K code, 64K data 256K unified SDRAM, DDR SDRAM
Efficeon 256-bit + SSE2 TM8300 900MHz--1.1GHz 128K code, 64K data 512K unified 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8600 900MHz--1.1GHz 128K code, 64K data 1M unified 100--166MHz DDR SDRAM + SPD 400MHz HyperTransport, AGP 1x/2x/4x
TM8620
TM8800