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Transmeta processors

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Revision as of 05:13, 15 April 2010 by Dank (talk | contribs)
Family Core Model Frequencies L1 Cache(s) L2 Cache Memory interface
Crusoe 128-bit TM3200 333--400MHz 64K code, 32K data none SDRAM
TM5400 500--700MHz 64K code, 64K data 256K unified SDRAM, DDR SDRAM
Efficeon 256-bit TM8600
TM8620
TM8800