Check out my first novel, midnight's simulacra!

X86 timing: Difference between revisions

From dankwiki
No edit summary
(link to sysfs properly)
(2 intermediate revisions by the same user not shown)
Line 1: Line 1:
* Linux clocksources vs clockevents
* Linux clocksources vs clockevents
* PIT -- Programmable Interval Timer (eg [http://en.wikipedia.org/wiki/Intel_8253 Intel 8253])
* PIT -- Programmable Interval Timer (eg [http://en.wikipedia.org/wiki/Intel_8253 Intel 8253])
* [[ACPI]] counter
* [[ACPI]] counter (PMTMR, Power Management Timer)
* LAPIC counter
* LAPIC counter
* HPET. Unprivileged programmability is limited by <tt>/proc/sys/dev/hpet/max-user-freq</tt> (in Hz):
* HPET. Unprivileged programmability is limited by <tt>/proc/sys/dev/hpet/max-user-freq</tt> (in Hz):
Line 7: Line 7:
64
64
[recombinator](0) $ </pre>
[recombinator](0) $ </pre>
* TSC since Pentium
==Time Stamp Counter==
Since the Pentium, a Time Stamp Counter has been made available in x86 processors. This is a register which is incremented either once per cycle (early implementations) or at some constant rate independent of SpeedStep, PowerNow!, [[ACPI|C-states]] and [[ACPI|P-states]] (P4 and future implementations), and is usually the most precise counter available to the x86 architecture. AMD made similar technology available on the K6 (introducing constant TSC with Barcelona/Phenom), as did Cyrix on the MII and Atmel on the AVR32 (via PCCNT, Performance Clock Count). On x86, use of the TSC is governed by the TSC (Time Stamp Disable) bit in the CR4 register. When this bit is set, reading the TSC is restricted to ring 0. Otherwise, all rings can read the TSC. Note that, even when using all 64 bits of the TSC, overflow is a real concern on modern processors.
* RDTSC reads the 64-bit TSC (an [[MSR]]) into EDX:EAX.
** Check [[CPUID]] function 0x00000001, EDX:4 to ensure RDTSC availability in the ISA
* RDTSCP is a serializing RDTSC, and thus unaffected by out-of-order execution. It also loads the lower 32 bits of the OS-managed MSR_TSC_AUX [[MSR]] into ECX.
** Check [[CPUID]] function 0x80000001, EDX:27 to ensure RDTSCP availability in the ISA
 
==Real Time Clocks==
==Real Time Clocks==
* [http://fxr.watson.org/fxr/source/Documentation/rtc.txt?v=linux-2.6 Linux docs]
* [http://fxr.watson.org/fxr/source/Documentation/rtc.txt?v=linux-2.6 Linux docs]
Line 28: Line 34:
* Multiple RTC's might exist in a machine, thus Linux's "RTC Class"
* Multiple RTC's might exist in a machine, thus Linux's "RTC Class"
** Each RTC gets a device node (by default, <tt>/dev/rtc*</tt>
** Each RTC gets a device node (by default, <tt>/dev/rtc*</tt>
** If [sysfs] is enabled, each gets an entry at <tt>/sys/class/rtc/*/</tt>:
** If [[sysfs]] is enabled, each gets an entry at <tt>/sys/class/rtc/*/</tt>:
<pre>[recombinator](0) $ ls /sys/class/rtc/rtc0/
<pre>[recombinator](0) $ ls /sys/class/rtc/rtc0/
date  device        name  since_epoch  time    wakealarm
date  device        name  since_epoch  time    wakealarm

Revision as of 22:40, 12 July 2012

  • Linux clocksources vs clockevents
  • PIT -- Programmable Interval Timer (eg Intel 8253)
  • ACPI counter (PMTMR, Power Management Timer)
  • LAPIC counter
  • HPET. Unprivileged programmability is limited by /proc/sys/dev/hpet/max-user-freq (in Hz):
[recombinator](1) $ cat /proc/sys/dev/hpet/max-user-freq 
64
[recombinator](0) $ 

Time Stamp Counter

Since the Pentium, a Time Stamp Counter has been made available in x86 processors. This is a register which is incremented either once per cycle (early implementations) or at some constant rate independent of SpeedStep, PowerNow!, C-states and P-states (P4 and future implementations), and is usually the most precise counter available to the x86 architecture. AMD made similar technology available on the K6 (introducing constant TSC with Barcelona/Phenom), as did Cyrix on the MII and Atmel on the AVR32 (via PCCNT, Performance Clock Count). On x86, use of the TSC is governed by the TSC (Time Stamp Disable) bit in the CR4 register. When this bit is set, reading the TSC is restricted to ring 0. Otherwise, all rings can read the TSC. Note that, even when using all 64 bits of the TSC, overflow is a real concern on modern processors.

  • RDTSC reads the 64-bit TSC (an MSR) into EDX:EAX.
    • Check CPUID function 0x00000001, EDX:4 to ensure RDTSC availability in the ISA
  • RDTSCP is a serializing RDTSC, and thus unaffected by out-of-order execution. It also loads the lower 32 bits of the OS-managed MSR_TSC_AUX MSR into ECX.
    • Check CPUID function 0x80000001, EDX:27 to ensure RDTSCP availability in the ISA

Real Time Clocks

[recombinator](0) $ cat /proc/driver/rtc 
rtc_time	: 07:43:30
rtc_date	: 2009-06-27
alrm_time	: **:00:00
alrm_date	: ****-**-**
alarm_IRQ	: no
alrm_pending	: no
24hr		: yes
periodic_IRQ	: no
update_IRQ	: no
HPET_emulated	: yes
DST_enable	: no
periodic_freq	: 1024
batt_status	: okay
[recombinator](0) $ 
  • Multiple RTC's might exist in a machine, thus Linux's "RTC Class"
    • Each RTC gets a device node (by default, /dev/rtc*
    • If sysfs is enabled, each gets an entry at /sys/class/rtc/*/:
[recombinator](0) $ ls /sys/class/rtc/rtc0/
date  device         name   since_epoch  time    wakealarm
dev   max_user_freq  power  subsystem    uevent
[recombinator](0) $ 

See Also