Root Complex Register Blocks (RCRBs)

What Problem Does an RCRB Address?

Refer to Figure 21-15 on page 766. Main memory is an extremely popular target. In addition to the processor, it is accessed by the graphics controller and is frequently accessed by PCI, PCI-X and PCI Express devices. This being the case, at a given moment in time, the Root Complex may simultaneously receive memory access requests through multiple ingress ports:

• The FSB interface.

• The graphics link.

• One or more Root Ports.

It should be obvious that a traffic director (labeled "Port/VC Arbitration") must be implemented within the Root Complex. In its simplest form, the Root Complex may implement a hardwired traffic director.

In addition to simply handling multiple simultaneous requests, the traffic director may also have to deal with QoS issues. Some of the memory access requesters may require faster access than others. The Root Complex Register Block would be used to program the memory controller's egress port logic regarding TC-to-VC mapping and the VC arbitration algorithm.

Additional Information on RCRBs

Additional information on RCRBs may be found in "RCRB" on page 957.