Direct Cache Access

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From [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction", section 3.1.10:

<~~code~~>When EAX is initialized to a value of 9, the [[cpuid|CPUID]] instruction returns DCA information in the EAX, EBX, ECX and EDX registers:

<blockquote>When EAX is initialized to a value of 9, the [[cpuid|CPUID]] instruction returns DCA information in the EAX, EBX, ECX and EDX registers:

EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)

*EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)

EBX: Reserved

*EBX: Reserved

ECX: Reserved

*ECX: Reserved

EDX: Reserved</~~code~~>

*EDX: Reserved</blockquote>

I've got a list of [[Hardware detritus#NICs|DCA-enabled NICs]].

DCA requires both hardware and software support. Its successor, [[DDIO]], does not.

==See Also==

*[http://www.stanford.edu/group/comparch/papers/huggahalli05.pdf "Direct Cache Access for High Bandwidth Network I/O"]

*[http://doi.ieeecomputersociety.org/10.1109/MC.2004.223 "TCP Onloading for Data Center Severs"]

*[http://www.eecs.umich.edu/techreports/cse/2004/CSE-TR-505-04.pdf "Analyzing NIC Overheads in Network-Intensive Workloads"]

~~==See Also==~~

[[Category: Hardware]]

[~~http~~:~~//www.stanford.edu/group/comparch/papers/huggahalli05.pdf "Direct Cache Access for High Bandwidth Network I/O"~~]

[[Category: x86]]

Direct Cache Access: Difference between revisions

Dank (talk | contribs)

@@ Line 1: / Line 1: @@
 From [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction", section 3.1.10:
-<code>When EAX is initialized to a value of 9, the [[cpuid|CPUID]] instruction returns DCA information in the EAX, EBX, ECX and EDX registers:
+<blockquote>When EAX is initialized to a value of 9, the [[cpuid|CPUID]] instruction returns DCA information in the EAX, EBX, ECX and EDX registers:
-EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)
+*EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)
-EBX: Reserved
+*EBX: Reserved
-ECX: Reserved
+*ECX: Reserved
-EDX: Reserved</code>
+*EDX: Reserved</blockquote>
 I've got a list of [[Hardware detritus#NICs|DCA-enabled NICs]].
+DCA requires both hardware and software support. Its successor, [[DDIO]], does not.
+==See Also==
+*[http://www.stanford.edu/group/comparch/papers/huggahalli05.pdf "Direct Cache Access for High Bandwidth Network I/O"]
+*[http://doi.ieeecomputersociety.org/10.1109/MC.2004.223 "TCP Onloading for Data Center Severs"]
+*[http://www.eecs.umich.edu/techreports/cse/2004/CSE-TR-505-04.pdf "Analyzing NIC Overheads in Network-Intensive Workloads"]
-==See Also==
+[[Category: Hardware]]
-[http://www.stanford.edu/group/comparch/papers/huggahalli05.pdf "Direct Cache Access for High Bandwidth Network I/O"]
+[[Category: x86]]