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MSI: Difference between revisions
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(Created page with "Message-signaled interrupts were introduced in PCI 2.2, and are present in all versions of PCIe. Rather than a distinct physical hardware line for interrupt delivery, MSIs are in-band. This cuts down on interconnect complexity, allows for multiple distinct interrupts per device (up to 32, though Windows supports only 16), and eliminates a performance hit previously necessary for DMA coherency. MSI-X, introduced in PCIe 3.0, allows up to 2048 interrupt numbers per device...") |
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MSI-X, introduced in PCIe 3.0, allows up to 2048 interrupt numbers per device. | MSI-X, introduced in PCIe 3.0, allows up to 2048 interrupt numbers per device. | ||
MSI requires per-package LAPICs to be present and enabled, but eliminates the need for per-bus I/O APICs. Intel's current LAPIC implementation, the x2APIC, can address 32-bit processor IDs and is set up using [[MSR|MSRs]]. | MSI requires per-package [[APIC|LAPICs]] to be present and enabled, but eliminates the need for per-bus I/O APICs. Intel's current LAPIC implementation, the x2APIC, can address 32-bit processor IDs and is set up using [[MSR|MSRs]]. | ||
Latest revision as of 03:41, 19 February 2023
Message-signaled interrupts were introduced in PCI 2.2, and are present in all versions of PCIe. Rather than a distinct physical hardware line for interrupt delivery, MSIs are in-band. This cuts down on interconnect complexity, allows for multiple distinct interrupts per device (up to 32, though Windows supports only 16), and eliminates a performance hit previously necessary for DMA coherency.
MSI-X, introduced in PCIe 3.0, allows up to 2048 interrupt numbers per device.
MSI requires per-package LAPICs to be present and enabled, but eliminates the need for per-bus I/O APICs. Intel's current LAPIC implementation, the x2APIC, can address 32-bit processor IDs and is set up using MSRs.
