SIMD: Difference between revisions
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SIMDnxm notation |
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[[File:Simd.jpeg|thumb|right|A 4-way SIMD unit]] | [[File:Simd.jpeg|thumb|right|A 4-way SIMD unit]] | ||
First introduced on the Illiac IV, and not to be confused with vector processing. | First introduced on the Illiac IV, and not to be confused with vector processing. SIMD-capable units are often taxonomized via <tt>SIMDnXm</tt> nomenclature, where '''n''' is the issue width and '''m''' is the channel width; a superscalar processor would be SIMDnX1, while a scalar SISD processor would be SIMD1X1. | ||
==Compilers and Assemblers== | ==Compilers and Assemblers== | ||
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* AMD64 Architecture Programmer’s Manual Volume 6: [http://support.amd.com/us/Processor_TechDocs/43479.pdf 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions] | * AMD64 Architecture Programmer’s Manual Volume 6: [http://support.amd.com/us/Processor_TechDocs/43479.pdf 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions] | ||
* Agner Fog's [http://www.agner.org/optimize/instruction_tables.pdf x86 Instruction Tables] | * Agner Fog's [http://www.agner.org/optimize/instruction_tables.pdf x86 Instruction Tables] | ||
* "[http://software.intel.com/en-us/blogs/2011/06/13/haswell-new-instruction-descriptions-now-available Haswell New Instruction Descriptions now Available]", Intel Software Developer Network, 2011-06-13 | |||
* General [[architecture]] page | * General [[architecture]] page | ||
[[Category: x86]] | [[Category: x86]] | ||