X86 timing: Difference between revisions
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* Linux clocksources vs clockevents | |||
* PIT -- Programmable Interval Timer (eg [http://en.wikipedia.org/wiki/Intel_8253 Intel 8253]) | * PIT -- Programmable Interval Timer (eg [http://en.wikipedia.org/wiki/Intel_8253 Intel 8253]) | ||
* [[ACPI]] counter | * [[ACPI]] counter (PMTMR, Power Management Timer) | ||
* LAPIC counter | * [[LAPIC]] counter | ||
* HPET. Unprivileged programmability is limited by <tt>/proc/sys/dev/hpet/max-user-freq</tt> (in Hz): | * HPET. Unprivileged programmability is limited by <tt>/proc/sys/dev/hpet/max-user-freq</tt> (in Hz): | ||
<pre>[recombinator](1) $ cat /proc/sys/dev/hpet/max-user-freq | <pre>[recombinator](1) $ cat /proc/sys/dev/hpet/max-user-freq | ||
64 | 64 | ||
[recombinator](0) $ </pre> | [recombinator](0) $ </pre> | ||
* TSC | ==Time Stamp Counter== | ||
* | Since the Pentium, a Time Stamp Counter has been made available in x86 processors. This is a register which is incremented either once per cycle (early implementations) or at some constant rate independent of SpeedStep, PowerNow!, [[ACPI|C-states]] and [[ACPI|P-states]] (P4 and future implementations), and is usually the most precise counter available to the x86 architecture. AMD made similar technology available on the K6 (introducing constant TSC with Barcelona/Phenom), as did Cyrix on the MII and Atmel on the AVR32 (via PCCNT, Performance Clock Count). On x86, use of the TSC is governed by the TSC (Time Stamp Disable) bit in the CR4 register. When this bit is set, reading the TSC is restricted to ring 0. Otherwise, all rings can read the TSC. Note that, even when using all 64 bits of the TSC, overflow is a real concern on modern processors. | ||
** [[ACPI]] standardized the <tt>cmos-rtc</tt> type, extending the Motorola MC146818 ([http://cateee.net/lkddb/web-lkddb/RTC_DRV_CMOS.html CONFIG_RTC_DRV_CMOS at the LKDD | * RDTSC reads the 64-bit TSC (an [[MSR]]) into EDX:EAX. | ||
** Check [[CPUID]] function 0x00000001, EDX:4 to ensure RDTSC availability in the ISA | |||
* RDTSCP is a serializing RDTSC, and thus unaffected by out-of-order execution. It also loads the lower 32 bits of the OS-managed MSR_TSC_AUX [[MSR]] into ECX. | |||
** Check [[CPUID]] function 0x80000001, EDX:27 to ensure RDTSCP availability in the ISA | |||
==Real Time Clocks== | |||
* [http://fxr.watson.org/fxr/source/Documentation/rtc.txt?v=linux-2.6 Linux docs] | |||
** [[ACPI]] standardized the <tt>cmos-rtc</tt> type, extending the Motorola MC146818 ([http://cateee.net/lkddb/web-lkddb/RTC_DRV_CMOS.html CONFIG_RTC_DRV_CMOS] at the LKDD) | |||
<pre>[recombinator](0) $ cat /proc/driver/rtc | <pre>[recombinator](0) $ cat /proc/driver/rtc | ||
rtc_time : 07:43:30 | rtc_time : 07:43:30 | ||
| Line 24: | Line 32: | ||
batt_status : okay | batt_status : okay | ||
[recombinator](0) $ </pre> | [recombinator](0) $ </pre> | ||
* Linux | * Multiple RTC's might exist in a machine, thus Linux's "RTC Class" | ||
** Each RTC gets a device node (by default, <tt>/dev/rtc*</tt> | |||
** If [[sysfs]] is enabled, each gets an entry at <tt>/sys/class/rtc/*/</tt>: | |||
<pre>[recombinator](0) $ ls /sys/class/rtc/rtc0/ | <pre>[recombinator](0) $ ls /sys/class/rtc/rtc0/ | ||
date device name since_epoch time wakealarm | date device name since_epoch time wakealarm | ||
dev max_user_freq power subsystem uevent | dev max_user_freq power subsystem uevent | ||
[recombinator](0) $ </pre> | [recombinator](0) $ </pre> | ||
==See Also== | |||
* Vojtech Pavlik's [http://lkml.org/lkml/2005/11/18/261 2005-11-18 LKML post] | |||
[[Category: x86]] | |||