Sandy Bridge

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Intel released Sandy Bridge in January 2011 as the major successor to [[Nehalem]]. Core i7, i5 and i3 variants were released simultaneously. Sandy Bridge can support an on-die integrated graphics processor. All Sandy Bridge processors to date use the new LGA 1155 socket ("Socket H2"), the successor to LGA 1156 ("Socket H"). The P67, H67, and H61 chipsets have been released to support Sandy Bridge, and are compatible with all current variants. It exhibits the ring-based bus designed for [[Larrabee]] and supports [[AVX]] instructions. Sandy Bridge processors (and their on-die IGP) are based on a 32nm process.

Intel released Sandy Bridge in January 2011 as the major successor to [[Nehalem]]. Core i7, i5 and i3 variants were released simultaneously. Sandy Bridge can support an on-die integrated graphics processor. All Sandy Bridge processors to date use the new LGA 1155 socket ("Socket H2"), the successor to LGA 1156 ("Socket H"). The P67, H67, and H61 chipsets have been released to support Sandy Bridge, and are compatible with all current variants. It exhibits the ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] instructions. Sandy Bridge processors (and their on-die IGP) are based on a 32nm process.

==Microarchitecture==

* As opposed to [[Nehalem]]'s [[Loop Stream Detector]], there's a simple, direct-mapped/LRU 1.5k μop cache

* Branch prediction can use multiple target sizes, depending on relative distance, and multiple history widths, depending on branch variance

===Last-Level Cache===

* Shared LLC remains "sliced" (NUMA), with slices distributed among cores

* L3 LLC moved out of ''uncore'' and now runs at core frequency

** Downclocked cores mean the L3 can be underclocked relative to the IGP!

* Cache pipeline is per-slice, rather than global to the cache

* L3 latencies reduced

===Interconnect===

* [[Larrabee]]'s ring interconnect connects the cores, IGP, LLC slices, media engine and System Agent (northbridge). 4 32-byte rings are used:

** Data, Request, ACK, Snoop

* Interconnect is built directly into L3 cache

==Family==

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==Processor Support==

===Northbridge ("System Agent")===

* Different clock and power plane

* Provides an IOMMU

* 16 PCIe 2.0 lanes

* Dual-channel DDR3

===IGP===

The 2000-series IGP has 6 execution units, while the 3000 has 12. Currently, 3000-series IGP's are reserved for K-series processors~~. The~~ P67 performance-oriented chipset cannot make use of the IGP, and requires a discrete graphics adapter.

The 2000-series IGP has 6 execution units, while the 3000 has 12. Currently, 3000-series IGP's are reserved for K-series processors (the P67 performance-oriented chipset cannot make use of the IGP, and requires a discrete graphics adapter). The IGP has limited locking on its clock -- the H67 chipset can control IGP multipliers.

Unlike [[Larrabee]]'s fully programmable shaders (suitable for [[GPGPU]]), Sandy Bridge IGP makes extensive use of fixed-function components. The instruction set is said to closely parallel the DirectX 10 API. There are a fixed 120 registers per thread, as opposed to the dynamically partitionable register file of previous Intel HD Graphics.

===MFX===

The Multi-Format Codec (MFX) engine is fixed functionality for high-performance, low-power transcoding. It features intensely parallel hardware.

===Chipset===

Sandy Bridge: Difference between revisions

Dank (talk | contribs)

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-Intel released Sandy Bridge in January 2011 as the major successor to [[Nehalem]]. Core i7, i5 and i3 variants were released simultaneously. Sandy Bridge can support an on-die integrated graphics processor. All Sandy Bridge processors to date use the new LGA 1155 socket ("Socket H2"), the successor to LGA 1156 ("Socket H"). The P67, H67, and H61 chipsets have been released to support Sandy Bridge, and are compatible with all current variants. It exhibits the ring-based bus designed for [[Larrabee]] and supports [[AVX]] instructions. Sandy Bridge processors (and their on-die IGP) are based on a 32nm process.
+Intel released Sandy Bridge in January 2011 as the major successor to [[Nehalem]]. Core i7, i5 and i3 variants were released simultaneously. Sandy Bridge can support an on-die integrated graphics processor. All Sandy Bridge processors to date use the new LGA 1155 socket ("Socket H2"), the successor to LGA 1156 ("Socket H"). The P67, H67, and H61 chipsets have been released to support Sandy Bridge, and are compatible with all current variants. It exhibits the ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] instructions. Sandy Bridge processors (and their on-die IGP) are based on a 32nm process.
+==Microarchitecture==
+* As opposed to [[Nehalem]]'s [[Loop Stream Detector]], there's a simple, direct-mapped/LRU 1.5k μop cache
+* Branch prediction can use multiple target sizes, depending on relative distance, and multiple history widths, depending on branch variance
+===Last-Level Cache===
+* Shared LLC remains "sliced" (NUMA), with slices distributed among cores
+* L3 LLC moved out of ''uncore'' and now runs at core frequency
+** Downclocked cores mean the L3 can be underclocked relative to the IGP!
+* Cache pipeline is per-slice, rather than global to the cache
+* L3 latencies reduced
+===Interconnect===
+* [[Larrabee]]'s ring interconnect connects the cores, IGP, LLC slices, media engine and System Agent (northbridge). 4 32-byte rings are used:
+** Data, Request, ACK, Snoop
+* Interconnect is built directly into L3 cache
 ==Family==
@@ Line 8: / Line 22: @@
 ==Processor Support==
+===Northbridge ("System Agent")===
+* Different clock and power plane
+* Provides an IOMMU
+* 16 PCIe 2.0 lanes
+* Dual-channel DDR3
 ===IGP===
-The 2000-series IGP has 6 execution units, while the 3000 has 12. Currently, 3000-series IGP's are reserved for K-series processors. The P67 performance-oriented chipset cannot make use of the IGP, and requires a discrete graphics adapter.
+The 2000-series IGP has 6 execution units, while the 3000 has 12. Currently, 3000-series IGP's are reserved for K-series processors (the P67 performance-oriented chipset cannot make use of the IGP, and requires a discrete graphics adapter). The IGP has limited locking on its clock -- the H67 chipset can control IGP multipliers.
+Unlike [[Larrabee]]'s fully programmable shaders (suitable for [[GPGPU]]), Sandy Bridge IGP makes extensive use of fixed-function components. The instruction set is said to closely parallel the DirectX 10 API. There are a fixed 120 registers per thread, as opposed to the dynamically partitionable register file of previous Intel HD Graphics.
+===MFX===
+The Multi-Format Codec (MFX) engine is fixed functionality for high-performance, low-power transcoding. It features intensely parallel hardware.
 ===Chipset===