Haswell: Difference between revisions

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	[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the split queue of [[Ivy Bridge]]. ]]		[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the SMT-split queue of [[Ivy Bridge]]. ]]
	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").