Sandy Bridge

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Intel released Sandy Bridge in January 2011 as the major successor to [[Nehalem]]. Core i7, i5 and i3 variants were released simultaneously. Sandy Bridge can support an on-die integrated graphics processor. All Sandy Bridge processors to date use the new LGA 1155 socket ("Socket H2"), the successor to LGA 1156 ("Socket H"). The P67, H67, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It exhibits the ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] instructions. Sandy Bridge processors (and their on-die IGP) are based on a 32nm process. [[Ivy Bridge]] is planned as a minor successor to Sandy Bridge, using a 22nm process.

==Architecture==

Sandy Bridge is the first Intel processor to support [[AVX]] instructions, including the 256-bit YMM0..15 registers and the [[VEX]] instruction encoding. XSAVE/XRSTOR operations will properly preserve and restore the full 256-bit registers. XMM [[SIMD|SSE]] registers map to the lower 128 bit of the corresponding YMM registers; the upper 128 bits will be zeroed out by SSE instructions.

Sandy Bridge is the first Intel processor to support [[AVX]] instructions, including the 256-bit YMM0..15 registers and the [[VEX]] instruction encoding.

* XSAVE/XRSTOR operations will properly preserve and restore the full 256-bit registers.

** May be called from any processor state. Use the XSAVE/XRSTOR memory areas, specified by [[MSR|MSRs]].

* XMM [[SIMD|SSE]] registers map to the lower 128 bit of the corresponding YMM registers; the upper 128 bits will be zeroed out by SSE instructions.

** Obviously, YMM-oriented [[AVX]] and XMM-oriented [[SSE]] instructions cannot be freely mixed

==Microarchitecture==

[[File:Sandybridgefrontend.jpg|thumb|right|Sandy Bridge frontend (contrast with [[Loop Stream Decoder]] of [[Nehalem]])]]

Sandy Bridge: Difference between revisions

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 Intel released Sandy Bridge in January 2011 as the major successor to [[Nehalem]]. Core i7, i5 and i3 variants were released simultaneously. Sandy Bridge can support an on-die integrated graphics processor. All Sandy Bridge processors to date use the new LGA 1155 socket ("Socket H2"), the successor to LGA 1156 ("Socket H"). The P67, H67, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It exhibits the ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] instructions. Sandy Bridge processors (and their on-die IGP) are based on a 32nm process. [[Ivy Bridge]] is planned as a minor successor to Sandy Bridge, using a 22nm process.
 ==Architecture==
-Sandy Bridge is the first Intel processor to support [[AVX]] instructions, including the 256-bit YMM0..15 registers and the [[VEX]] instruction encoding. XSAVE/XRSTOR operations will properly preserve and restore the full 256-bit registers. XMM [[SIMD|SSE]] registers map to the lower 128 bit of the corresponding YMM registers; the upper 128 bits will be zeroed out by SSE instructions.
+Sandy Bridge is the first Intel processor to support [[AVX]] instructions, including the 256-bit YMM0..15 registers and the [[VEX]] instruction encoding.
+* XSAVE/XRSTOR operations will properly preserve and restore the full 256-bit registers.
+** May be called from any processor state. Use the XSAVE/XRSTOR memory areas, specified by [[MSR|MSRs]].
+* XMM [[SIMD|SSE]] registers map to the lower 128 bit of the corresponding YMM registers; the upper 128 bits will be zeroed out by SSE instructions.
+** Obviously, YMM-oriented [[AVX]] and XMM-oriented [[SSE]] instructions cannot be freely mixed
 ==Microarchitecture==
 [[File:Sandybridgefrontend.jpg|thumb|right|Sandy Bridge frontend (contrast with [[Loop Stream Decoder]] of [[Nehalem]])]]