Sandy Bridge

Line 2:

[[File:Sandybridgedie.jpg|thumb|right|Sandy Bridge die]]

Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The P67, H67, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).

==Architecture==

[[File:Sandy-bridge-nehalem-bulldozer.png|thumb|right|Sandy Bridge, [[Nehalem]], and [[Bulldozer]] fetch/dec units]]

Sandy Bridge is the first Intel processor to support [[AVX]] instructions, including the 256-bit YMM0..15 registers and the [[VEX]] instruction encoding.

* XSAVE/XRSTOR operations will properly preserve and restore the full 256-bit registers.

Sandy Bridge: Difference between revisions

Dank (talk | contribs)

@@ Line 2: / Line 2: @@
 [[File:Sandybridgedie.jpg|thumb|right|Sandy Bridge die]]
 Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The P67, H67, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).
 ==Architecture==
+[[File:Sandy-bridge-nehalem-bulldozer.png|thumb|right|Sandy Bridge, [[Nehalem]], and [[Bulldozer]] fetch/dec units]]
 Sandy Bridge is the first Intel processor to support [[AVX]] instructions, including the 256-bit YMM0..15 registers and the [[VEX]] instruction encoding.
 * XSAVE/XRSTOR operations will properly preserve and restore the full 256-bit registers.