Sandy Bridge: Difference between revisions
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** Augments 8-way/32K VIPT L1 icache (completely distinct hardware) | ** Augments 8-way/32K VIPT L1 icache (completely distinct hardware) | ||
* L1TLB: 16 full-assoc dedicated per-thread large [[pages]], 128 4-way core-shared small [[pages]] | * L1TLB: 16 full-assoc dedicated per-thread large [[pages]], 128 4-way core-shared small [[pages]] | ||
** '''(FIXME: in HT-incapable processor models, do you get 16 or 32 large pages per core?)''' | |||
* Branch prediction can use multiple target sizes, depending on relative distance, and multiple history widths, depending on branch variance | * Branch prediction can use multiple target sizes, depending on relative distance, and multiple history widths, depending on branch variance | ||
* 2 dataload/addrstore ports are now dataload/addrload/addrstore | * 2 dataload/addrstore ports are now dataload/addrload/addrstore | ||