Check out my first novel, midnight's simulacra!
Direct Cache Access: Difference between revisions
From dankwiki
No edit summary |
No edit summary |
||
| Line 3: | Line 3: | ||
*EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h) | *EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h) | ||
*EBX: Reserved | *EBX: Reserved | ||
ECX: Reserved | *ECX: Reserved | ||
EDX: Reserved</blockquote> | *EDX: Reserved</blockquote> | ||
I've got a list of [[Hardware detritus#NICs|DCA-enabled NICs]]. | I've got a list of [[Hardware detritus#NICs|DCA-enabled NICs]]. | ||
Revision as of 12:17, 27 June 2009
From Intel Application Note 485, "Intel Processor Identification and the CPUID Instruction", section 3.1.10:
When EAX is initialized to a value of 9, the CPUID instruction returns DCA information in the EAX, EBX, ECX and EDX registers:
- EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)
- EBX: Reserved
- ECX: Reserved
- EDX: Reserved
I've got a list of DCA-enabled NICs.
