Appendix D. Class Codes

This appendix lists the class codes, sub-class codes, and programming interface byte definitions currently provided in the 2.3 PCI specification.

Table D-1. Defined Class Codes

Class	Description
00h	Function built before class codes were defined (in other words: before rev 2.0 of the PCI spec).
01h	Mass storage controller.
02h	Network controller.
03h	Display controller.
04h	Multimedia device.
05h	Memory controller.
06h	Bridge device.
07h	Simple communications controllers.
08h	Base system peripherals.
09h	Input devices.
0Ah	Docking stations.
0Bh	Processors.
0Ch	Serial bus controllers.
0Dh	Wireless controllers.
0Eh	Intelligent IO controllers.
0Fh	Satellite communications controllers.
10h	Encryption/Decryption controllers.
11h	Data acquisition and signal processing controllers.
12h-FEh	Reserved.
FFh	Device does not fit any of the defined class codes.

Table D-2. Class Code 0 (PCI rev 1.0)

Sub-Class	Prog. I/F	Description
00h	00h	All devices other than VGA.
01h	01h	VGA-compatible device.

Table D-3. Class Code 1: Mass Storage Controllers

Sub-Class	Prog. I/F	Description
00h	00h	SCSI controller.
01h	xxh	IDE controller. See Table D-20 on page 1031 for definition of Programming Interface byte.
02h	00h	Floppy disk controller.
03h	00h	IPI controller.
04h	00h	RAID controller.
05h	20h	ATA controller with single DMA.
	30h	ATA controller with chained DMA.
80h	00h	Other mass storage controller.

Table D-4. Class Code 2: Network Controllers

Sub-Class	Prog. I/F	Description
00h	00h	Ethernet controller.
01h	00h	Token ring controller.
02h	00h	FDDI controller.
03h	00h	ATM controller.
04h	00h	ISDN Controller.
05h	00h	WorldFip controller.
06h		PICMG 2.14 Multi Computing. For information on the use of the Programming Interface Byte, see the PICMG 2.14 Multi Computing Specification (http://www.picmg.com).
80h	00h	Other network controller.

Table D-5. Class Code 3: Display Controllers

Sub-Class	Prog. I/F	Description
00h	00h	VGA-compatible controller, responding to memory addresses 000A0000h through 000BFFFFh (Video Frame Buffer), and IO addresses 03B0h through 3BBh, and 03C0h-through-03DFh and all aliases of these addresses.
	01h	8514-compatible controller, responding to IO address 02E8h and its aliases, 02EAh and 02EFh.
01h	00h	XGA controller.
02h	00h	3D Controller.
80h	00h	Other display controller.

Table D-6. Class Code 4: Multimedia Devices

Sub-Class	Prog. I/F	Description
00h	00h	Video device.
01h	00h	Audio device.
02h	00h	Computer Telephony device.
80h	00h	Other multimedia device.

Table D-7. Class Code 5: Memory Controllers

Sub-Class	Prog. I/F	Description
00h	00h	RAM memory controller.
01h	00h	Flash memory controller.
80h	00h	Other memory controller.

Table D-8. Class Code 6: Bridge Devices

Sub-Class	Prog. I/F	Description
00h	00h	Host/PCI bridge.
01h	00h	PCI/ISA bridge.
02h	00h	PCI/EISA bridge.
03h	00h	PCI/Micro Channel bridge.
04h	00h	PCI/PCI bridge.
	01h	Subtractive decode PCI-to-PCI bridge. Supports subtractive decode in addition to normal PCI-to-PCI functions. For a detailed discussion of this bridge type, refer to the MindShare PCI System Architecture book, Fourth Edition (published by Addison-Wesley).
05h	00h	PCI/PCMCIA bridge.
06h	00h	PCI/NuBus bridge.
07h	00h	PCI/CardBus bridge.
08h	xxh	RACEway bridge. RACEway is an ANSI standard (ANSI/VITA 5-1994) switching fabric. Bits 7:1 of the Interface bits are reserved, read-only and return zeros. Bit 0 is read-only and, if 0, indicates that the bridge is in Transparent mode, while 1 indicates that it's in End-Point mode.
09h	40h	Semi-transparent PCI-to-PCI bridge with the primary PCI bus side facing the system host processor.
	80h	Semi-transparent PCI-to-PCI bridge with the secondary PCI bus side facing the system host processor.
0Ah	00h	InfiniBand-to-PCI host bridge.
80h	00h	Other bridge type.

Table D-9. Class Code 7: Simple Communications Controllers

Sub-Class	Prog. I/F	Description
00h	00h	Generic XT-compatible serial controller.
	01h	16450-compatible serial controller.
	02h	16550-compatible serial controller.
	03h	16650-compatible serial controller.
	04h	16750-compatible serial controller.
	05h	16850-compatible serial controller.
	06h	16950-compatible serial controller.
01h	00h	Parallel port.
	01h	Bi-directional parallel port.
	02h	ECP 1.X-compliant parallel port.
	03h	IEEE 1284 controller.
	FEh	IEEE 1284 target device (not a controller).
02h	00h	Multiport serial controller.
03h	00h	Generic modem.
	01h	Hayes-compatible modem, 16450-compatible interface. BAR 0 maps the modem's register set. The register set can be either memory- or IO-mapped (as indicated by the type of BAR).
	02h	Hayes-compatible modem, 16550-compatible interface. BAR 0 maps the modem's register set. The register set can be either memory- or IO-mapped (as indicated by the type of BAR).
	03h	Hayes-compatible modem, 16650-compatible interface. BAR 0 maps the modem's register set. The register set can be either memory- or IO-mapped (as indicated by the type of BAR).
	04h	Hayes-compatible modem, 16750-compatible interface. BAR 0 maps the modem's register set. The register set can be either memory- or IO-mapped (as indicated by the type of BAR).
04h	00h	GPIB (IEEE 488.1/2) controller.
05h	00h	Smart Card.
80h	00h	Other communications device.

Table D-10. Class Code 8: Base System Peripherals

Sub-Class	Prog. I/F	Description
00h	00h	Generic 8259 programmable interrupt controller (PIC).
	01h	ISA PIC.
	02h	EISA PIC.
	10h	IO APIC. Base Address Register 0 is used to request a minimum of 32 bytes of non-Prefetchable memory. Two registers within that space are located at Base + 00h (IO Select Register) and Base + 10h (IO Window Register). For a full description of the use of these registers, refer to the data sheet for the Intel 8237EB in the 82420/82430 PCIset EISA Bridge Databook #290483-003.
	20h	IO(x) APIC interrupt controller.
01h	00h	Generic 8237 DMA controller.
	01h	ISA DMA controller.
	02h	EISA DMA controller.
02h	00h	Generic 8254 timer.
	01h	ISA system timers.
	02h	EISA system timers.
03h	00h	Generic RTC controller.
	01h	ISA RTC controller.
04h	00h	Generic PCI Hot-Plug controller.
80h	00h	Other system peripheral.

Table D-11. Class Code 9: Input Devices

Sub-Class	Prog. I/F	Description
00h	00h	Keyboard controller.
01h	00h	Digitizer (pen).
02h	00h	Mouse controller.
03h	00h	Scanner controller.
04h	00h	Generic gameport controller.
	10h	Gameport controller. A gameport controller with a Programming Interface = 10h indicates that any Base Address registers in this function that request/assign IO address space, the registers in that IO space conform to the standard "legacy" game ports. The byte at offset 00h in an IO region behaves as a legacy gameport interface where reads to the byte return joystick/gamepad information and writes to the byte start the RC timer. The byte at offset 01h is an alias of the byte at offset 00h. All other bytes in an IO region are unspecified and can be used in vendor unique ways.
80h	00h	Other input controller.

Table D-12. Class Code A: Docking Stations

Sub-Class	Prog. I/F	Description
00h	00h	Generic docking station.
80h	00h	Other type of docking station.

Table D-13. Class Code B: Processors

Sub-Class	Prog. I/F	Description
00h	00h	386.
01h	00h	486.
02h	00h	Pentium.
10h	00h	Alpha.
20h	00h	PowerPC.
30h	00h	MIPS
40h	00h	Co-processor.

Table D-14. Class Code C: Serial Bus Controllers

Sub-Class	Prog. I/F	Description
00h	00h	Firewire (IEEE 1394).
	10h	IEEE 1394 using 1394 OpenHCI spec.
01h	00h	ACCESS.bus.
02h	00h	SSA (Serial Storage Architecture).
03h	00h	USB (Universal Serial Bus) controller using Universal Host Controller spec.
	10h	USB (Universal Serial Bus) controller using Open Host Controller spec.
	80h	USB (Universal Serial Bus) controller with no specific programming interface.
	FEh	USB device (not Host Controller).
04h	00h	Fibre Channel.
05h	00h	SMBus (System Management Bus).
06h	00h	InfiniBand.
07h	00h	IPMI SMIC Interface. The register interface definitions for the Intelligent Platform Management Interface Sub-Class 07h) are in the IPMI specification.
	01h	IPMI Kybd Controller Style Interface
	02h	IPMI Block Transfer Interface
08h	00h	SERCOS Interface Standard (IEC 61491). There is no register level definition for the SERCOS Interface standard. For more information see IEC 61491.
09h	00h	CANbus.
80h	00h	Other type of Serial Bus Controller.

Table D-15. Class Code D: Wireless Controllers

Sub-Class	Interface	Meaning
00	00h	iRDA compatible controller
01h	00h	Consumer IR controller
10h	00h	RF controller
11h	00h	Bluetooth.
12h	00h	Broadband.
80h	00h	Other type of wireless controller

Table D-16. Class Code E: Intelligent IO Controllers

Sub-Class	Interface	Meaning
00h	xxh	Intelligent IO controller adhering to the I2O Architecture spec. The spec can be downloaded from ftp.intel.com/pub/IAL/i2o/.
	00h	Message FIFO at offset 40h.
80h	00h	Other type of Intelligent IO Controller.

Table D-17. Class Code F: Satellite Communications Controllers

Sub-Class	Interface	Meaning
01h	00h	TV
02h	00h	Audio
03h	00h	Voice
04h	00h	Data
80h	00h	Other type of Satellite Communications Controller.

Table D-18. Class Code 10h: Encryption/Decryption Controllers

Sub-Class	Interface	Meaning
00h	00h	Network and computing Encrypt/Decrypt.
10h	00h	Entertainment Encrypt/Decrypt.
80h	00h	Other Encrypt/Decrypt.

Table D-19. Class Code 11h: Data Acquisition and Signal Processing Controllers

Sub-Class	Interface	Meaning
00h	00h	DPIO modules.
01h	00h	Performance counters.
10h	00h	Communications synchronization plus time and frequency test/measurement.
20h	00h	Management card.
80h	00h	Other Data Acquisition and Signal Processing Controllers.

Table D-20. Definition of IDE Programmer's Interface Byte Encoding

Bit(s)	Description
0	Operating mode (primary).
1	Programmable indicator (primary).
2	Operating mode (secondary).
3	Programmable indicator (secondary).
6:4	Reserved. Hardwired to zero.
7	Master IDE device.

Note: The SIG document PCI IDE Controller Specification completely describes the layout and meaning of bits 0 through 3 in the Programming Interface byte. The document Bus Master Programming Interface for IDE ATA Controllers describes the meaning of bit 7 in the Programming Interface byte. While the PCI 2.1 spec stated that this document could be obtained via FAX by calling (408)741-1600 and requesting document 8038, that reference was removed from the 2.3 spec.