Example Enhanced Configuration Access

Refer to Figure 20-9 on page 737. The following x86 code sample will cause the Root Complex to perform a read from Bus 4, Device 0, Function 0's Vendor ID configuration register. The example assumes that the 256MB-aligned base address of the Enhanced Configuration memory-mapped IO range is 50000000h:

mov   ax,[50400000];memory-mapped IO read

• Address bits 63:28 indicates the upper 36 bits of the 256MB-aligned base address of the overall Enhanced Configuration address range (in this case, 000000005h).

• Address bits 27:20 select the target bus (in this case, 4).

• Address bits 19:15 select the target device (in this case, 0) on the bus.

• Address bits 14:12 select the target function (in this case, 0) within the device.

• Address bits 11:2 selects the target dword (in this case, 0) within the selected function's configuration space.

• Address bits 1:0 define the start byte location within the selected dword (in this case, 0).

The processor initiates a 2-byte memory read from memory locations 50400000h and 50400001h on its FSB. The request is latched by the Host/PCI bridge in the Root Complex. It decodes the address and determines that it is a configuration read request for the first two bytes in dword 0, function 0, device 0, bus 4. The remainder of the operation is the same as that described in the previous section.