PCI Express Enhanced Configuration Mechanism
Description
Refer to Table 20-1 on page 732. Each function's 4KB configuration space starts at a 4KB-aligned address within the 256MB memory space set aside as configuration space:
Address bits 63:28 indicates the 256MB-aligned base address of the overall Enhanced Configuration address range. Address bits 27:20 select the target bus (1-of-256). Address bits 19:15 select the target device (1-of-32) on the bus. Address bits 14:12 select the target function (1-of-8) within the device. Address bits 11:2 selects the target dword (1-of-1024) within the selected function's configuration space. Address bits 1:0 define the start byte location within the selected dword.
Some Rules
A Root Complex design is not required to support an access to the enhanced configuration memory space that crosses a dword address boundary (i.e., the access straddles two adjacent memory dwords.
In addition, some processor types can perform a series of memory accesses as an atomic, locked, transaction series. A Root Complex design is not required to support an access to the enhanced configuration memory space using this locking mechanism.
This being the case, software should avoid both of the scenarios just described unless it is known that the Root Complex implementation being used supports the translation.
Table 20-1. Enhanced Configuration Mechanism Memory-Mapped IO Address Range|
A[63:28] | Upper bits of the 256MB-aligned base address of the 256MB memory-mapped IO address range allocated for the Enhanced Configuration Mechanism.
The manner in which the base address is allocated is implementation-specific. It is supplied to the OS by system firmware. | A[27:20] | Target Bus Number (1-of-256). | A[19:15] | Target Device Number (1-of-32). | A[14:12] | Target Function Number (1-of-8). | A[11:2] | A[11:8] is the upper four bits of the target Dword Number (1-of-1024). | A[7:2] is the lower six bits of the target Dword Number. | A[1:0] | Along with the access size, defines the Byte Enable setting. |
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