New pages

From dankwiki
New pages
Hide registered users | Hide bots | Show redirects
  • 00:21, 12 March 2023A Rack of One's Own (hist | edit) ‎[13,147 bytes]Dank (talk | contribs) (Created page with "<b>dankblog! 2023-03-11, 1709 EST, at the danktower</b> i've never owned "enterprise-class" hardware, nor even really worked with it much. i'm of the Google school: buy COTS by lots, count on it breaking, and work around the failures. xeons and (more recently) epycs never seemed price-competitive (though i seriously considered the former for my 2016 workstation build), especially given their reduced clocks. as amd's threadripper emerged, they weren...") originally created as "A Supercomputer of One's Own"
  • 09:02, 19 February 2023Iproute (hist | edit) ‎[111 bytes]Dank (talk | contribs) (Created page with "iproute2, usually invoked as <tt>ip</tt>, is the command-line interface to Linux's unified netlink backend.")
  • 09:01, 19 February 2023Alexey Kuznetsov (hist | edit) ‎[55 bytes]Dank (talk | contribs) (Created page with "He sees, he sees the evil hand of the big-endian mafia.")
  • 03:41, 19 February 2023MSI (hist | edit) ‎[709 bytes]Dank (talk | contribs) (Created page with "Message-signaled interrupts were introduced in PCI 2.2, and are present in all versions of PCIe. Rather than a distinct physical hardware line for interrupt delivery, MSIs are in-band. This cuts down on interconnect complexity, allows for multiple distinct interrupts per device (up to 32, though Windows supports only 16), and eliminates a performance hit previously necessary for DMA coherency. MSI-X, introduced in PCIe 3.0, allows up to 2048 interrupt numbers per device...")
  • 03:30, 19 February 2023RSS (hist | edit) ‎[1,291 bytes]Dank (talk | contribs) (Created page with "Receiver-Side Scaling is a function of some NICs where traffic is divided into one or more hardware RX queues, each with their own MSI. These MSI numbers can then be associated with different cores, creating parallelism in network interrupt handling. If the device must not reorder traffic within a flow, it is generally necessary that all packets from the same flow hit the same core, so the RX queue is typically chosen via a hash over the L3 and L4 addresses. This mea...")
  • 22:17, 18 February 2023100GbE (hist | edit) ‎[1,918 bytes]Dank (talk | contribs) (Created page with "100 Gigabit Ethernet achieves 100Gbs data rates using the Ethernet Layer 2 protocol.")
  • 14:03, 11 February 2023Transfiguration (hist | edit) ‎[6,233 bytes]Dank (talk | contribs) (Created page with "dankblog! 2023-02-11, 0903 EST, at the danktower")
  • 19:37, 6 February 2023NAPI (hist | edit) ‎[681 bytes]Dank (talk | contribs) (Created page with "The "New API" for Linux NIC drivers introduced around 2001, NAPI is initiated by a NIC's hardware interrupt, but then disables interrupts and polls the card for a period. This can significantly reduce the CPU load compared to a pure interrupt-driven solution. NAPI largely obsoletes the "interrupt coalescing" features of some NICs. It is strictly receive-side. ==The NAPI path== A NIC has some number of hardware RX queues, each of which is mapped to an interrupt number an...")
  • 06:07, 27 January 202392mm fans (hist | edit) ‎[747 bytes]Dank (talk | contribs) (Created page with " {|class="wikitable sortable" ! Model !! RPM || dB(A) !! m³/h !! mm H₂O !! Color !! Power(W) !! Comments |- | San Ace 92 9CRA0912P0G001 || 13300 || 81 || 348 || 168.4 || Black || 108 || 76mm thick |- | NF-A9 PWM || 2000 || 22.8 || 78.9 || 2.28 || Brown || 1.2 || |- | NF-A9 PWM chromax.swap || 2000 || 22.8 || 78.9 || 2.28 || Black || 1.2 || |- | NF-B9 redux-1600 PWM || 1600 || 17.6 || 64.3 || 1.61 || Grey || 0.96 || |- | NF-A9x14 HS-PWM chromax.black.swap || 2500 ||...")
  • 00:54, 22 January 2023DDIO (hist | edit) ‎[1,423 bytes]Dank (talk | contribs) (Created page with "Data Direct I/O is an [https://www.intel.com/content/www/us/en/io/data-direct-i-o-technology.html Intel technology] allowing PCIe devices to interact directly with local processor LLCs (Last Level Caches). It supersedes and extends Direct Cache Access, and is present on E7 Xeons of the second generation and later, and all E5 Xeons. ==Configuration== Model-specific register 0xc8b controls which LLC ways are used by DDIO. There is currently no CPUID element co...")
  • 07:50, 12 January 2023Control Groups (hist | edit) ‎[3,317 bytes]Dank (talk | contribs) (Created page with "aka cgroupsv2 aka unified cgroups. Control Groups v2 were unveiled in Linux 4.5 as a means of controlling resource allocation across groups of tasks. Unlike the previous implementation of control groups (introduced in Linux 2.6.24), these cgroups would be under a single hierarchy, usually mounted with a <tt>cgroup2</tt>-type virtual filesystem at <tt>/sys/fs/cgroup</tt>. systemd makes fundamental use of cgroups (and indeed, last I checked it couldn't run without them...")
  • 03:52, 1 January 2023Ergot (hist | edit) ‎[17,249 bytes]Dank (talk | contribs) (Created page with "* '''Ergot''': fungi of the genus Claviceps. All Claviceps species are ergot. The most well-known member is Claviceps purpurea (Latin ''purpuro'', purple, "to adorn/beautify"), the rye ergot fungus, which is parasitic on grasses and cereals (especially rye). ** A Claviceps spore infects a flowering grass or cereal's floret. Upon connection to the vascular bundle, soft white sphacelia tissue develops. This hardens and dries into a sclerotium in the destroyed floret's husk...")