Dual-Simplex

The PCI Express serial bus is a dual-simplex bus (see Figure A-3 on page 965), unlike the parallel-based PCI bus where the start and end of a transfer can be seen on the same bus as shown in Figure A-1 on page 962.

This architecture requires the requester to transmit a "Request" for data transfer on one transmit pair, while it receives the "Completion" response on the receive signal pair. Considering that the response time can widely vary, developers need to be able to set the analyzer to filter the received and the transmitted data independent of each other.

Also the agents on the two ends of the PCI express link may be equally capable of being requesters and completers. This allows a transaction type to be generated in either direction on the link at different times. Therefore, being able to specify the trigger and data capture on both buses independently is very important, and users must specify the direction in order to trigger on the proper transfer they intend to view.

The two signal pairs from the host to the device are referred to as Upstream (towards the host processor) and Downstream (away from the host processor). The analyzer should be able to sample both signal pairs and trigger on occurrences of patterns on either pair or just one, per user defined settings.