Threadripper L3 CPUID Strangeness: Difference between revisions

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and to a great deal of misery and frustration, and daydreams of becoming a stripper because you sure as shit don't want to be a programmer. writing this is about as fun as bobbing for apples in a ~~sunsearing~~ bucket of curdling possum shit. every time a new [[Architecture|microarchitecture]] employed a different cache size, thus mandating a new [[CPUID]] number, your discovery failed. in fact, my very first PR at GOOG was to add descriptors for whatever rhodium-crusted CapEx-demolishing Xeons we were fielding, as apparently 70,000 engineers had been content until then to just read "Couldn't discover cache size for processor type FOO!" twice in their logs every time they ran a binary before bitching on ''eng-misc'' for six hours or cosplaying at unionizing. perhaps it was lost in the 400KB of messages about your single-core text search program being unable to elect a [https://en.wikipedia.org/wiki/Paxos_(computer_science) paxos] leader. google-sized problems, baybee!

and to a great deal of misery and frustration, and daydreams of becoming a stripper because you sure as shit don't want to be a programmer. writing this is about as fun as bobbing for apples in a sunseared bucket of curdling possum shit. every time a new [[Architecture|microarchitecture]] employed a different cache size, thus mandating a new [[CPUID]] number, your discovery failed. in fact, my very first PR at GOOG was to add descriptors for whatever rhodium-crusted CapEx-demolishing Xeons we were fielding, as apparently 70,000 engineers had been content until then to just read "Couldn't discover cache size for processor type FOO!" twice in their logs every time they ran a binary before bitching on ''eng-misc'' for six hours or cosplaying at unionizing. perhaps it was lost in the 400KB of messages about your single-core text search program being unable to elect a [https://en.wikipedia.org/wiki/Paxos_(computer_science) paxos] leader. google-sized problems, baybee!

Thankfully, both Intel and AMD unfucked themselves late in the aughts, or unfucked in any case this small fuckgrove, and introduced more sensibly-structured CPUID results. [https://www.amd.com/system/files/TechDocs/25481.pdf AMD provides] CPUID leaf 0x80000006, "L2/L3 Cache and TLB Identification". The EDX register returns "L3 Cache Identifiers", structured thusly:

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-and to a great deal of misery and frustration, and daydreams of becoming a stripper because you sure as shit don't want to be a programmer. writing this is about as fun as bobbing for apples in a sunsearing bucket of curdling possum shit. every time a new [[Architecture|microarchitecture]] employed a different cache size, thus mandating a new [[CPUID]] number, your discovery failed. in fact, my very first PR at GOOG was to add descriptors for whatever rhodium-crusted CapEx-demolishing Xeons we were fielding, as apparently 70,000 engineers had been content until then to just read "Couldn't discover cache size for processor type FOO!" twice in their logs every time they ran a binary before bitching on ''eng-misc'' for six hours or cosplaying at unionizing. perhaps it was lost in the 400KB of messages about your single-core text search program being unable to elect a  [https://en.wikipedia.org/wiki/Paxos_(computer_science) paxos] leader. google-sized problems, baybee!
+and to a great deal of misery and frustration, and daydreams of becoming a stripper because you sure as shit don't want to be a programmer. writing this is about as fun as bobbing for apples in a sunseared bucket of curdling possum shit. every time a new [[Architecture|microarchitecture]] employed a different cache size, thus mandating a new [[CPUID]] number, your discovery failed. in fact, my very first PR at GOOG was to add descriptors for whatever rhodium-crusted CapEx-demolishing Xeons we were fielding, as apparently 70,000 engineers had been content until then to just read "Couldn't discover cache size for processor type FOO!" twice in their logs every time they ran a binary before bitching on ''eng-misc'' for six hours or cosplaying at unionizing. perhaps it was lost in the 400KB of messages about your single-core text search program being unable to elect a  [https://en.wikipedia.org/wiki/Paxos_(computer_science) paxos] leader. google-sized problems, baybee!
 Thankfully, both Intel and AMD unfucked themselves late in the aughts, or unfucked in any case this small fuckgrove, and introduced more sensibly-structured CPUID results. [https://www.amd.com/system/files/TechDocs/25481.pdf AMD provides] CPUID leaf 0x80000006, "L2/L3 Cache and TLB Identification". The EDX register returns "L3 Cache Identifiers", structured thusly:

Threadripper L3 CPUID Strangeness: Difference between revisions

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