[ Team LiB ] [SYMBOL] [A] [B] [C] [D] [E] [F] [G] [H] [I] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] PA/RISC executable code  Parity Error Response  2nd  Pause command  2nd  Pausing a Driver  PCI Bus Driver  2nd  3rd  PCI Bus PM Interface Specification  PCI Data Structure  PCI Express Capabilities Register  PCI Express Capability ID Register  PCI Express Capability Register Set  PCI Express Endpoint  PCI Interrupt Signaling  PCI PM  PCI power management  2nd  3rd  PCI-Compatible Error Reporting  PCI-to-PCI Address Decode-Related Registers   PCI-to-PCI bridge  2nd  3rd  PCI-to-PCI bridge terminology  Physical Slot ID  PM Capabilities (PMC) Register  PM Capability Registers  PM Control/Status (PMCSR) Register  PM Event (PME) Context  PM Registers  PM_Active_State_Request_L1  PM_Enter_L1 DLLP  PM_Enter_L23  PM_Request_Ack  PMC Register  PMCSR Register  PME Clock bit  PME Context  PME#  PME_En bit  PME_Status bit  PME_Support field  Polarity Inversion  2nd  Port  2nd  3rd  Port Arbitration  2nd  3rd  4th  5th  6th  7th  8th  Port Arbitration Table  2nd  3rd  Port VC Capability Register 1  Port VC Control Register  Port VC Status Register  POST  Power Budget Register Set  Power Budgeting Capability Register  Power Budgeting Data Register  Power Budgeting Enhanced Capability Header  Power Indicator  Power IRP  power management  2nd  3rd  Power Management DLLP Packet  Power Management Messages  Power Management Policy Owner  power management register set  Power_Indicator_Blink Message  Power_Indicator_Off Message  Power_Indicator_On Message  PowerPC  PowerState field  Pre-emphasis  2nd  Prefetchable Attribute bit  2nd  prefetchable memory  2nd  Prefetchable Memory Base and Limit registers  Primary bus  Primary Bus Number register  Primary Discard Timeout  Primitives  Primitives, hot-plug  2nd  Producer/Consumer Model  Programming Interface byte  2nd

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