[ Team LiB ] [SYMBOL] [A] [B] [C] [D] [E] [F] [G] [H] [I] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] L0  L0 State  L0s state  L0s State  L1 ASPM  2nd  3rd  L1 ASPM Negotiation  L1 State  L2 State  L2/L3 Ready state  2nd  L3 State  Lane  2nd  3rd  4th  5th  6th  7th  Lane Reversal  Lane-to-Lane De-Skew  Last DW Byte Enables  2nd  Latency Timer Registers  LCRC  2nd  3rd  4th  Legacy Endpoint  2nd  3rd  4th  5th  6th  Link  2nd  3rd  4th  5th  Link Capabilities Register  Link Capability Register  Link Control Register  Link Errors  Link Flow Control-Related Errors  Link Power Management  Link Status Register  Link Training and Initialization  2nd  3rd  Link Width  2nd  3rd  4th  Low-priority VC Arbitration  LTSSM

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